The present invention is related to a data processing system having input/output channels, control units each for controlling peripheral devices, and a dynamic switch between the channels and the control units, and is more particularly related to reporting state changes through the dynamic switch from particular ones of the control units to the channels or from particular ones of the channels to the control units.
Various switches such as cross-point switches are known for establishing connections between data lines. Such switches are useful in establishing point-to-point connections between an input/output (I/O) channel of a data processing system and an I/O peripheral device or control unit.
Georgiou, Parallel Interface Switching Mechanism, pp 4690-4692, IBM Technical Disclosure Bulletin, Vol. 27, No. 8, Jan., 1985, discloses utilizing high-speed cross-point switching chips in multiple parallel interface switching mechanisms. A controller is referred to but not shown which is used to set up connections on the switching chips in order to establish paths between channels and control units.
U.S. Pat. No. 4,074,142 to Jackson for Optical Cross-Point Switch issued Feb. 14, 1978 and discloses an optical cross-point switch for connecting any of a multiplicity of input signals to any of a multiplicity of output lines. Electrical signals are converted to optical signals by light emitting diodes. The light from each light emitting diode is focused on photosensor means to convert the optical signals back to electrical signals. An input and output address decoding circuit selects one light emitting diode to be coupled to one photosensor to make a switch connection. The address information is transmitted to the optical switch via an address bus.
U.S. Pat. No. 4,562,533 to Hodel et al. for Data Communications System to System Adapter issued Dec. 31, 1985 and discloses a data processing system having a dynamic channel exchange and a plurality of central systems. Each of the central systems has at least one serial channel control processor. The dynamic channel exchange provides switching logic for permitting each of the plurality of central systems access to a plurality of peripherals coupled to the dynamic channel exchange. The data processing system further includes an adapter which is connected to the dynamic channel exchange for providing communications between any pair of central systems.
U.S. Pat. No. 4,605,928 to Georgiou for Fault-Tolerant Array of Cross-Point Switching Matrices issued Aug. 12, 1986 and discloses a cross-point switch in which it is possible to have bi-directional operation for allowing data flow in both directions.
U.S. Pat. No. 4,630,045 to Georgiou for Controller for a Cross-Point Switching Matrix issued Dec. 16, 1986 and discloses a switching matrix controller which interprets a request for connection or disconnection, determines if it is possible, selects a path through the matrix and sends control signals to the matrix to make the connection or disconnection. The status of the switching array is checked when making the connection or disconnection.
U.S. Pat. No. 4,635,250 to Georgiou for Full-Duplex One-Sided Cross-Point Switch issued Jan. 6, 1987 and discloses a one-sided cross-point switching chip which may be operated in a full duplex mode wherein the direction of information flow or electrical signals on the internal vertical lines or the interconnection lines can be in different directions, depending upon which external lines are to be interconnected.
U.S. Pat. No. 4,641,302 to Miller for High Speed Packet Switching Arrangement issued Feb. 3, 1987 and discloses a circuit arrangement for switching serial data packets through a network to one of a plurality of possible outgoing lines. The incoming serial data is in packets wherein each packet includes a header portion containing an address indicative of which one of a plurality of outgoing lines the data packet should be routed to.
U.S. Pat. No. 4,692,917 to Fujioka for Packet Switching System issued Sep. 8, 1987 and discloses a packet switching system having a packet handler for analyzing a header of each incoming packet and deciding the outgoing route of the packet. The packet also includes a packet closing flag which causes the packet handler to release the connection.
U.S. Pat. No. 4,703,487 to Haselton et al. for Burst-Switching Method for an Integrated Communications System issued Oct. 27, 1987 and U.S. Pat. No. 4,771,419 to Graves et al. for Method of and Switch for Switching Information issued Sep. 13, 1988. Both of these patents disclose switching networks for switching data wherein a header contains an address for making a connection and a termination character or characters for breaking the connection.
Systems are known in which the status of one element is sent to a remote location. U.S. Pat. No. 4,225,918 to Beadle et al for "System for Entering Information Into and Taking it From a Computer From a Remote Location" issued Sep. 30, 1980 and discloses a system for transmitting binary instruction or data words to or from a computer by control from a home base remote from the computer site. The system includes a special purpose microcomputer directly connected to the main computer console which returns to the home base a rapidly integrated and updated pulse train representative of the status of all console lights.
U.S. Pat. No. 4,257,100 to Syrbe et al for "Electronic Data Processing System for Real Time Data Processing" issued Mar. 17, 1981 and discloses an electronic data processing system having a ring bus. In the case of a fault, the operability of all bus line segments, each of which connects two neighboring stations, is tested by means of test messages. The bus line status is determined and reported to all stations still connected together.
U.S. Pat. No. 4,490,785 to Strecker et al for "Dual Path Bus Structure for Computer Interconnection" issued Dec. 25, 1984 and discloses a bus structure for use in a computer network wherein each host device in the network connects to the bus paths through a port. Path selection is carried out by the port which, when a path failure is detected, automatically switches to an alternate good path upon detection of the failure, all without host involvement.
U.S. Pat. No. 4,494,241 to Mayoux for "Installation For the Transmission of Information by an Optical Bus Line" issued Jan. 15, 1985 and discloses a bus line installation for the transmission of information between a plurality of transmitters and a plurality of receivers.
U.S. Pat. No. 4,551,718 to Cookson et al for "Method and Apparatus for Transmitting Status Information Between Remote Locations" issued Nov. 5, 1985 and discloses a system for transmitting status information from a first location to a remote second location and includes a monitoring device at the first location for monitoring the state of a plurality of relays or other devices that are capable of being in either an active or inactive state. A processor produces a first signal indicative of a change of state of any relay from the inactive to the active state.
U.S. Pat. No. 4,654,784 to Campanini for "Circuit Arrangement for Routing Signals Between a Master-Slave Pair of Controlling Processors and Several Master-Slave Pairs of Controlled Processing Units" issued Mar. 31, 1987 and discloses a plurality of switching modules in a telecommunication system wherein the switch modules switch to alternate links in the event of a malfunction.